On Nov. 9, 2026, Google announced two more systems in its eighth generation of Tensor Processing Units: TPU 8tx and TPU 8i Max. In a Google Cloud blog post by Amin Vahdat, the company describes TPU 8tx as a confidential-computing inference system built on the same silicon as TPU 8t. It describes TPU 8i Max as two TPU 8i chips in a single package. Google says this is the first time it has introduced four TPU systems in one year.

Neither system is a new chip design, as ServeTheHome points out. Both reuse the 8t and 8i silicon Google announced earlier this generation and change what surrounds it: the host processors and network in one case, the package in the other. For data center operators and the utilities that serve them, the 8i Max claim to note is that Google says it fits twice the silicon into the existing rack footprint.

The performance figures below come from Google's own announcement unless otherwise attributed. They are company claims and have not been independently benchmarked.

The Context: Eighth-Generation TPUs

Google's post says its TPUs now have nearly 100 customers. It also repeats the company's earlier claims for the base eighth-generation parts: up to 2.7x better training performance and 80% better inference price performance than the previous generation, for TPU 8t and 8i respectively.

TechPowerUp's coverage reprints Google's announcement text and makes the same claims. It does not add independent analysis.

TPU 8tx: Same Silicon, Confidential Hosts

Google says TPU 8tx is built for confidential inference. It uses the same accelerator silicon as TPU 8t, paired with 5th Gen AMD EPYC host processors. Confidential computing generally means data stays protected while it is being processed, not only when it is stored or moving over a network. Google presents 8tx as its answer for customers who want that protection on AI inference workloads.

The company makes two performance claims for 8tx. First, it says the system delivers up to 2x lower latency than TPU 8t. Second, it says the confidential-computing protections come with a near-zero performance penalty. Google credits the latency claim in part to its Boardfly network.

ServeTheHome adds detail on the hosts. It reports that 8tx uses dual-socket EPYC Turin servers, and that the 128 PCIe Gen5 lanes on those hosts were chosen to match the PCIe Gen5 x16 links on the TPU 8t accelerators. On the network, ServeTheHome says Boardfly has a maximum network-hop diameter of seven, compared with sixteen for a torus topology. A smaller hop diameter means data crosses fewer links in the worst case to get from one chip to another.

ServeTheHome also calls the design a win for AMD's EPYC line, because AMD server CPUs are serving as hosts in an accelerator system that does not use AMD accelerators. That is the outlet's view.

TPU 8i Max: Two Chips, One Package

TPU 8i Max puts two TPU 8i chips on one package. Compared with a single TPU 8i, Google says that doubles compute, on-chip SRAM and high-bandwidth memory (HBM) bandwidth.

ServeTheHome gives specific figures for the 8i Max package: 384 GB of HBM, 17.2 TB/s of HBM bandwidth and 768 MB of SRAM. It says the HBM capacity is about a third more than TPU 8i. Note what that implies: capacity rises by roughly a third, while bandwidth, by Google's account, doubles. These numbers are ServeTheHome's. They did not appear in Google's post, so readers should treat them as the outlet's reporting until Google publishes a specification sheet.

Google's post says memory bandwidth quickly becomes the bottleneck when many AI agents work across an entire codebase or hours of video at once. By doubling HBM bandwidth per package, Google is aiming 8i Max at that constraint.

Why the Rack Footprint Claim Matters

The 8i Max claim that matters most for facilities is about density, not speed. Google says that because the package fits twice the silicon into the existing rack footprint, data centers can deploy significantly more computing power per square foot and per watt.

That statement has two parts. "More compute per square foot" follows from putting two chips where one used to go. "More compute per watt" is an efficiency claim. Google's post does not say how much power an 8i Max rack draws compared with an 8i rack. It also gives no rack-level power, cooling or floor-space figures. Twice the silicon in the same footprint could mean more power and heat per rack even if each unit of compute uses less energy. The materials reviewed do not settle that question.

For operators planning halls, and for utilities and local officials judging load requests from AI campuses, the useful takeaway is narrow: Google says it is packing more accelerator silicon into the rack positions it already has. The sources do not provide the numbers needed to estimate how that changes power demand at a given site.

What Was Not Announced

The Google post did not give an availability date, regions or pricing for either system in the text reviewed. It also did not name customers using TPU 8tx or TPU 8i Max. Neither ServeTheHome nor TechPowerUp reports a launch date.

What Happens Next

None of the three sources gives a scheduled, on-the-record next step for TPU 8tx or TPU 8i Max. Google's announcement includes no general-availability date, preview window or pricing. DataCenterFeed will report availability, regions and published specifications, including any rack-level power figures, when Google releases them.

Sources